Altera Transceiver PHY IP Core - Manual (Page 199)

PHY for PCIe (PIPE) Output Data to the PHY MAC
This section describes the PIPE output signals. These signals are driven from the PCS to the PHY MAC.
This interface is compliant to the appropriate PIPE interface specification.
Table 8-5: Avalon-ST RX Inputs
Signal Name Direction Description
pipe_rxdata[[(31,16
or
8)-
1:0]
Output
This is RX parallel data driven from the PCS to the MAC
PHY. The ready latency on this interface is 0, so that the
MAC must be able to accept data as soon as the PHY
comes out of reset. Width is 8 or 16 for Gen1 and Gen2.
Width is 32 for Gen3.
Transmission is little endian. For example, for Gen3,
words are transmitted in the following order:
• PIPE word 0:
pipe_rxdata[7:0]
• PIPE word 1:
pipe_rxdata[15:8]
• PIPE word 2:
pipe_rxdata[23:16]
• PIPE word 3:
pipe_rxdata[31:24]
pipe_rxdatak[(3,2
or
1)-
1:0]
Output
Data and control indicator for the source data. When 0,
indicates that
pipe_rxdata
is data, when 1, indicates
that
pipe_rxdata
is control.
Bit[0] corresponds to byte 0. Bit[]1 corresponds to byte
1, and so on.
rx_blk_start[3:0]
Output For Gen3 operation, indicates the block starting byte
location in the received 32-bits data of the 130-bits block
data. Data reception must start in bits [7:0] of the 32-bit
data word, so that the only valid value is 4’b0001.
rx_sync_hdr[1:0]
Output
For Gen3, indicates whether the 130-bit block being
transmitted is a Data or Control Ordered Set Block. The
following encodings are defined:
• 2'b10: Data block
• 2'b01: Control Ordered Set block
This valued is read when
rx_blk_start
= 4'b0001.
Refer to “Section 4.2.2.1. Lane Level Encoding” in the PCI
Express Base Specification, Rev. 3.0 for a detailed
explanation of data transmission and reception using
128b/130b encoding and decoding.
UG-01080
2015.01.19
PHY for PCIe (PIPE) Output Data to the PHY MAC 8-11
PHY IP Core for PCI Express (PIPE) Altera Corporation
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