Altera Transceiver PHY IP Core User Manual
Page 480
Name
Dir
Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
Bit-Slip Gearbox Feature Synchronizer
rx_10g_bitslip
[
Input
No
User control bit-slip in the RX Gearbox. Slips one
bit per rising edge pulse.
tx_10g_bitslip
[7
Input
No
TX bit-slip is controlled by
tx_bitslip
port.
Shifts the number of bit location specified by
tx_
bitslip
. The maximum shift is
64b/66b
rx_10g_clr_errblk_
count
[
Input
No
For the 10GBASE-R protocol, asserted to clear the
error block counter which counts the number of
times the RX state machine enters the RX error
state.
BER
rx_10g_highber
[
Output
No
For the 10GBASE-R protocol, status signal
asserted to indicate a bit error ratio of >10
–4
. A
count of 16 in 125us indicates a bit error ratio of >
10
–4
. Once asserted, it remains high for at least 125
us.
rx_10g_clr_highber_
cnt
[
Input
No
For the 10GBASE-R protocol, status signal
asserted to clear the BER counter which counts the
number of times the BER state machine enters the
BER_BAD_SH state. This signal has no effect on
the operation of the BER state machine.
PRBS
rx_10g_prbs_done
Output
When asserted, indicates the verifier has aligned
and captured consecutive PRBS patterns and the
first pass through a polynomial is complete.
rx_10g_prbs_err
Output
When asserted, indicates an error only after the
rx_10g_prbs_done
signal has been asserted. This
signal pulses for every error that occurs. An error
can only occur once per word. This signal
indicates errors for both the PRBS and pseudo-
random patterns.
rx_10g_prbs_err_clr
Input
When asserted, clears the PRBS pattern and de-
asserts the
rx_10g_prbs_done
signal.
UG-01080
2015.01.19
10G PCS Interface
14-69
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation