Altera Transceiver PHY IP Core - Manual (Page 401)

Name Direction Description
tx_parallel_data[43:0] Input PCS TX parallel data representing 4, 11-
bit words. Used when you enable the
Standard datapath. Refer to Table
13-20 for bit definitions. Refer to Table
13-21 various parameterizations.
rx_parallel_data[63:0] Output PCS RX parallel data, representing 4, 16-
bit words. Used when you enable the
Standard datapath. Refer to Table 13-22
for bit definitions. Refer to Table 13-23
for various parameterizations.
TX and RX serial ports
tx_serial_data[-1:0] Output TX differential serial output data.
rx_serial_data[-1:0] Input RX differential serial output data.
Control and Status ports
rx_seriallpbken[-1:0] Input When asserted, the transceiver enters
serial loopback mode. Loopback drives
serial TX data to the RX interface.
rx_set_locktodata[-1:0] Input When asserted, programs the RX CDR to
manual lock to data mode in which you
control the reset sequence using the
rx_
set_locktoref
and
rx_set_
locktodata
. Refer to “Transceiver Reset
Sequence” in Transceiver Reset Control
in Arria V Devices for more information
about manual control of the reset
sequence.
rx_set_locktoref[-1:0] Input When asserted, programs the RX CDR to
manual lock to reference mode in which
you control the reset sequence using the
rx_set_locktoref
and
rx_set_
locktodata
. Refer to Refer to
“Transceiver Reset Sequence” in
Transceiver Reset Control in Arria V
Devices for more information about
manual control of the reset sequence.
pll_locked[
-1:0]
Output When asserted, indicates that the PLL is
locked to the input reference clock.
rx_is_lockedtodata[-1:0] Output When asserted, the CDR is locked to the
incoming data.
13-26 Common Interface Ports
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
Send Feedback