Altera Transceiver PHY IP Core - Manual (Page 7)

Interfaces for Deterministic Latency PHY........................................................................................... 11-15
Data Interfaces for Deterministic Latency PHY..................................................................................11-16
Clock Interface for Deterministic Latency PHY................................................................................. 11-19
Optional TX and RX Status Interface for Deterministic Latency PHY............................................11-20
Optional Reset Control and Status Interfaces for Deterministic Latency PHY..............................11-21
Register Interface and Descriptions for Deterministic Latency PHY.............................................. 11-22
Dynamic Reconfiguration for Deterministic Latency PHY...............................................................11-27
Channel Placement and Utilization for Deterministic Latency PHY ............................................. 11-28
SDC Timing Constraints........................................................................................................................ 11-29
Simulation Files and Example Testbench for Deterministic Latency PHY ....................................11-30
Stratix V Transceiver Native PHY IP Core.......................................................12-1
Device Family Support for Stratix V Native PHY.................................................................................12-2
Performance and Resource Utilization for Stratix V Native PHY......................................................12-3
Parameter Presets.......................................................................................................................................12-3
Parameterizing the Stratix V Native PHY..............................................................................................12-4
General Parameters for Stratix V Native PHY ..........................................................................12-4
PMA Parameters for Stratix V Native PHY...............................................................................12-6
Standard PCS Parameters for the Native PHY........................................................................12-13
10G PCS Parameters for Stratix V Native PHY ......................................................................12-29
Interfaces for Stratix V Native PHY .....................................................................................................12-46
Common Interface Ports for Stratix V Native PHY............................................................... 12-46
Standard PCS Interface Ports.....................................................................................................12-53
10G PCS Interface........................................................................................................................12-58
×6/×N Bonded Clocking.........................................................................................................................12-69
xN Non-Bonded Clocking......................................................................................................................12-73
SDC Timing Constraints of Stratix V Native PHY ............................................................................12-74
Dynamic Reconfiguration for Stratix V Native PHY......................................................................... 12-75
Simulation Support..................................................................................................................................12-76
Slew Rate Settings.................................................................................................................................... 12-76
Arria V Transceiver Native PHY IP Core.........................................................13-1
Device Family Support..............................................................................................................................13-2
Performance and Resource Utilization...................................................................................................13-3
Parameterizing the Arria V Native PHY................................................................................................ 13-3
General Parameters....................................................................................................................................13-3
PMA Parameters........................................................................................................................................13-4
TX PMA Parameters..................................................................................................................... 13-5
TX PLL Parameters........................................................................................................................13-6
RX PMA Parameters..................................................................................................................... 13-8
Standard PCS Parameters.......................................................................................................................13-10
Phase Compensation FIFO.........................................................................................................13-12
Byte Ordering Block Parameters............................................................................................... 13-13
Byte Serializer and Deserializer..................................................................................................13-14
8B/10B........................................................................................................................................... 13-15
Rate Match FIFO..........................................................................................................................13-15
Word Aligner and BitSlip Parameters...................................................................................... 13-18
Altera Transceiver PHY IP Core User Guide TOC-7
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