Altera Transceiver PHY IP Core - Manual (Page 381)

Table 13-4: TX PMA Parameters
Parameter Range Description
Enable TX PLL dynamic
reconfiguration
On/Off When you turn this option On, you can dynamically
reconfigure the PLL. This option is also required to
simulate TX PLL reconfiguration. If you turn this option
On, the Quartus II Fitter prevents PLL merging by
default; however, you can specify merging using the
XCVR_TX_PLL_RECONFIG_GROUP
QSF assignment.
Use external TX PLL On/Off When you turn this option On, the Native PHY does not
automatically instantiate a TX PLL. Instead, you must
instantiate an external PLL and connect it to the
ext_
pll_clk[
-1 : 0]
port of the Arria V Native PHY.
Use the Arria V Transceiver PLL IP Core to instantiate a
CMU PLL. Use Altera Phase-Locked Loop (ALTERA_
PLL) Megafunction to instantiate a fractional PLL.
Number of TX PLLs 1–4 Specifies the number of TX PLLs that can be used to
dynamically reconfigure channels to run at multiple data
rates. If your design does not require transceiver TX PLL
dynamic reconfiguration, set this value to 1. The number
of actual physical PLLs that are implemented depends on
the selected clock network. Each channel can
dynamically select between n PLLs, where n is the
number of PLLs specified for this parameter.
Note: Refer to Transceiver Clocking in Arria V
Devices chapter for more details.
Main TX PLL logical
index
0–3 Specifies the index of the TX PLL used in the initial
configuration.
Number of TX PLL
reference clocks
1–5 Specifies the total number of reference clocks that are
used by all the PLLs.
Related Information
Transceiver Clocking in Arria V Devices
TX PLL Parameters
This section allows you to define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a
separate tab for each TX PLL.
13-6 TX PLL Parameters
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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