Reduced mif creation, Register-based write, Reduced mif creation -42 – Altera Transceiver PHY IP Core User Manual
Page 559: Register-based write -42
Reduced MIF Creation
The procedure described here is an alternative way to generate a reduced MIF file. You can also use the
xcvr_diffmifgen
Utility. Follow these steps to generate a reduced MIF:
1. Determine the content differences between the original MIF and the reconfigured MIF. For this
example, assume there are bit differences at offset 5 and offset 20. These offsets reside in the
PMA-TX
and
PMA-RX
sections of the MIF.
2. Use a text editor to create a new reduced MIF file. In this example, we will call the reduced MIF
reduced_mif.mif. Copy the
WIDTH
,
DEPTH
,
ADDRESS_RADIX
,
DATA_RADIX
and
CONTENT BEGIN
lines
from the original MIF to reduced_mif.mif.
3. Copy offsets 0-3 as described
from the original MIF to reduced_mif.mif. The reconfigu‐
ration MIF must always include these lines.
4. Copy all offsets of the
PMA-TX
and
PMA-RX
sections from the reconfigured MIF to reduced_mif.mif.
5. Copy the
End of MIF
opcode offset and
END
; from the original MIF to reduced_mif.mif.
6. Renumber reduced_mif.mif sequentially and update the
DEPTH
variable with the new value. The new
value equals the number offsets in reduced_mif.mif.
You can now use reduced_mif.mif to reconfigure the transceiver.
You can create a reduced MIF from the following two MIFs:
• Original MIF—contains the transceiver settings that were specified during the initial compilation
• Reconfigured MIF—contains the new transceiver settings. You generate the reconfigured MIF by
modifying the original transceiver settings. For example, if the original compilation specifies a clock
divider value of 1 and the reconfigured compilation specifies a clock divider value of 2, the MIF files
reflect that change. The reduced MIF contains only the changed content. In this example, the
difference between the two MIFs would be the clock divider value.
Changing Transceiver Settings Using Register-Based Reconfiguration
This section describes changing the transceiver settings.
In register-based mode, you use a sequence of Avalon-MM writes and reads to update individual
transceiver settings. The following section describes how to perform a register-based reconfiguration read
and write.
Register-Based Write
Complete the following steps, using a state machine as an example, to perform a register-based write:
1. Read the
control and status
register
busy
bit (bit 8) until it is clear.
2. Write the logical channel number of the channel to be updated to the
logical channel number
register.
3. Write the <feature> offset address.
4. Write the appropriate data value to the data register.
5. Write the
control and status
register
write
bit to 1’b1.
6. Read the
control and status
register busy bit. Continue to read the
busy
bit while its value is one.
7. When
busy
= 0, the Transceiver Reconfiguration Controller has updated the logical channel specified
in Step 2 with the data specified in Step 3.
16-42
Reduced MIF Creation
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview