Phy for pcie (pipe) optional status interface, Phy for pcie (pipe) serial data interface, Phy for pcie (pipe) optional status interface -14 – Altera Transceiver PHY IP Core User Manual
Page 202: Phy for pcie (pipe) serial data interface -14
Add the following command to force Timequest analysis at 62.5 MHz.
create_generated_clock -name clk_g1 -source [get_ports {pll_refclk}] \
-divide_by 8 -multiply_by 5 -duty_cycle 50 -phase 0 -offset 0 [get_nets \
{*pipe_nr_inst|transceiver_core|inst_sv_xcvr_native|inst_sv_pcs| \
ch[*].inst_sv_pcs_ch|inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout}] -add
#creating false paths between these clock groups
set_clock_groups -asynchronous -group [get_clocks clk_g3]
set_clock_groups -asynchronous -group [get_clocks clk_g1]
set_clock_groups -asynchronous -group [get_clocks *pipe_nr_inst| \
transceiver_core|inst_sv_xcvr_native|inst_sv_pcs|ch[*]. \
inst_sv_pcs_ch|inst_sv_hssi_8g_tx_pcs|wys|clkout]
PHY for PCIe (PIPE) Optional Status Interface
This section describes the signals the optional status signals.
Table 8-8: Status Signals
Signal Name
(5)
Direction
Signal Name
tx_ready
Output
When asserted, indicates that the TX interface has
exited the reset state and is ready to transmit.
rx_ready
Output
When asserted, indicates that the RX interface has
exited the reset state and is ready to receive.
pll_locked[
-1:0]
Output
When asserted, indicates that the TX PLL is locked to
the input reference clock. This signal is asynchronous.
rx_is_lockedtodata[
Output
When asserted, the receiver CDR is in to lock-to-data
mode. When deasserted, the receiver CDR lock mode
depends on the
rx_locktorefclk
signal level.
rx_is_lockedtoref[
Output
Asserted when the receiver CDR is locked to the input
reference clock. This signal is asynchronous.
rx_syncstatus[
Output
Indicates presence or absence of synchronization on
the RX interface. Asserted when word aligner identifies
the word alignment pattern or synchronization code
groups in the received data stream.
rx_signaldetect[
1:0]
Output
When asserted indicates that the lane detects a sender
at the other end of the link.
PHY for PCIe (PIPE) Serial Data Interface
This section describes the differential serial TX and RX connections to FPGA pins.
(5)
<n> is the number of lanes. <d> is the deserialization factor. < p> is the number of PLLs.
8-14
PHY for PCIe (PIPE) Optional Status Interface
UG-01080
2015.01.19
Altera Corporation
PHY IP Core for PCI Express (PIPE)