Altera Transceiver PHY IP Core User Manual
Page 355
Name
Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
rx_std_bitslipboun-
darysel[5
Output No
This signal operates when the word aligner
is in bitslip word alignment mode. It
reports the number of bits that the RX
block slipped to achieve deterministic
latency.
rx_std_runlength_err[
1:0]
Output No
When asserted, indicates a run length
violation. Asserted if the number of
consecutive 1s or 0s exceeds the number
specified in the parameter editor GUI.
rx_st_wa_patternalign
Input
No
Active when you place the word aligner in
manual mode. In manual mode, you align
words by asserting rx_st_wa_patternalign.
rx_st_wa_patternalign is edge sensitive.
For more information refer to the Word
Aligner section in the Transceiver Architec‐
ture in Arria V Devices.
rx_std_wa_a1a2size[
1:0]
Input
No
Used for the SONET protocol. Assert
when the A1 and A2 framing bytes must
be detected. A1 and A2 are SONET
backplane bytes and are only used when
the PMA data width is 8 bits.
rx_std_bitslip[
Input
No
Used when word aligner mode is bitslip
mode. For every rising edge of the
rx_std_
bitslip
signal, the word boundary is
shifted by 1 bit. Each bitslip removes the
earliest received bit from the received data.
This is an asynchronous input signal and
inside there is a synchronizer to
synchronize it with
rx_pma_clk/rx_
clkout
.
PRBS
rx_std_prbs_done
Output Yes
When asserted, indicates the verifier has
aligned and captured consecutive PRBS
patterns and the first pass through a
polynomial is complete. The generator has
restarted the polynomial.
UG-01080
2015.01.19
Standard PCS Interface Ports
12-57
Stratix V Transceiver Native PHY IP Core
Altera Corporation