Altera Transceiver PHY IP Core User Manual
Page 31
Device Family
Support
Arria V ST devices-Soft PCS and Hard PMA
Final
Arria V GZ
Final
Stratix IV GT devices–Soft PCS and Hard PMA
Final
Stratix V devices–Hard PCS and PMA
Final
Other device families
No support
Note: For speed grade information, refer to “Transceiver Performance Specifications” in the DC and
Switching Characteristics chapter in the Stratix IV Handbook for Stratix IV devices or Stratix V
Device Datasheet.
Related Information
•
•
10GBASE-R PHY Performance and Resource Utilization for Stratix IV
Devices
Because the 10GBASE-R PHY is implemented in hard logic it uses less than 1% of the available ALMs,
memory, primary and secondary logic registers. The following table lists the typical expected device
resource utilization for duplex channels using the current version of the Quartus II software targeting a
Stratix IV GT device. The numbers of combinational ALUTs, logic registers, and memory bits are
rounded to the nearest 100.
Table 3-5: 10GBASE-R PHY Performance and Resource Utilization—Stratix IV GT Device
Channels
Combinational ALUTs
Logic Registers (Bits)
Memory Bits
1
5200
4100
4700
4
15600
1300
18800
10
38100
32100
47500
10GBASE-R PHY Performance and Resource Utilization for Arria V GT
Devices
The following table lists the resource utilization when targeting an Arria V (5AGTFD7K3F4015) device.
Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus
II software v12.1 release for 28 nm device families and upcoming device families. The numbers of ALMs
and logic registers are rounded up to the nearest 100.
Note: For information about Quartus II resource utilization reporting, refer to Fitter Resources Reports
in the Quartus II Help.
UG-01080
2015.01.19
10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices
3-7
10GBASE-R PHY IP Core
Altera Corporation