1gbe parameters, 1gbe parameters -9 – Altera Transceiver PHY IP Core User Manual
Page 65
Parameter Name
Options
Description
Enable FEC status ports
On/Off
When you turn this option the core includes the
rx_block_lock
,
rx_parity_good
,
rx_parity_
invalid
, and
tx_frame
signals.
Note: This parameter is not implemented in
the early access release.
Related Information
Analog Parameters Set Using QSF Assignments
1GbE Parameters
The 1GbE parameters allow you to specify options for the 1GbE mode.
Table 4-8: 1Gb Ethernet Parameters
Parameter Name
Options
Description
Enable 1Gb Ethernet protocol
On/Off
When you turn this option On, the core includes
the GMII interface and related logic.
Enable SGMII bridge logic
On/Off
When you turn this option On, the core includes
the SGMII clock and rate adaptation logic for
the PCS. You must turn this option On if you
enable 1G mode.
Enable IEEE 1588 Precision Time
Protocol
On/Off
When you turn this option On, the core includes
a module in the PCS to implement the IEEE
1588 Precision Time Protocol.
PHY ID (32 bit)
32-bit value
An optional 32-bit value that serves as a unique
identifier for a particular type of PCS. The
identifier includes the following components:
• Bits 3-24 of the Organizationally Unique
Identifier (OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which
is 0x00000000.
PHY Core version (16 bits)
16-bit value
This is an optional 16-bit value identifies the
PHY core version.
Reference clock frequency
125.00 MHz
62.50 MHz
Specifies the clock frequency for the
1GBASE-KR PHY IP Core. The default is 125
MHz.
Related Information
on page 3-30
UG-01080
2015.01.19
1GbE Parameters
4-9
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation