Altera Transceiver PHY IP Core - Manual (Page 485)

In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to
Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY
reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and
dynamic reconfiguration of the channel and PLLs.
You specify the initial configuration when you parameterize the IP core. The Transceiver Native PHY IP
Core connects to the “Transceiver Reconfiguration Controller IP Core” to dynamically change reference
clocks, PLL connectivity, and the channel configurations at runtime.
Related Information
• Transceiver PHY Reset Controller IP Core on page 17-1
• Transceiver Reconfiguration Controller IP Core Overview on page 16-1
Cyclone Device Family Support
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 15-1: Device Family Support
Device Family Support
Cyclone V devices Final
Other device families No support
Cyclone V Native PHY Performance and Resource Utilization
Because the Standard PCS and PMA are implemented in hard logic, the Cyclone V Native PHY IP Core
requires minimal resources.
Parameterizing the Cyclone V Native PHY
Complete the following steps to configure the Cyclone V Native PHY IP Core in:
1. Under Tools > IP Catalog, select Arria V as the device family.
2. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY, select Cyclone V Native PHY.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
4. Click Finish to generate your customized Cyclone V Native PHY IP Core.
15-2 Cyclone Device Family Support
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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