Altera Transceiver PHY IP Core User Manual
Page 256
Name
Value
Description
Enable TX bitslip
On/Off
The bit slip feature allows you to slip the
transmitter side bits before they are sent to the
gearbox. The maximum number of bits slipped is
equal to the ((FPGA fabric-to-transceiver
interface width) – 1). For example, if the FPGA
fabric-to-transceiver interface width is 64 bits, the
bit slip logic can slip a maximum of 63 bits. Each
channel has 5 bits to determine the number of
bits to slip. The value specified on the TX bitslip
bus indicates the number of bit slips. Effectively,
each value shifts the word boundary by one bit.
For example, a TX bitslip value of 1 on a 64bit
FPGA interface width shifts the word boundary
by 1 bit. That is, bit[63] from the first word and
bit[62:0] are concatenated to form a 64 bit word
(bit[62:0] from the second word, bit[63] from the
first word LSB).
This option is only available for the Standard and
10G datapaths.
Enable RX bitslip
On/Off
When enabled, the wordaligner operates in bitslip
mode. This option is available for Stratix V and
Arria V GZ devices using the 10G datapath.
Enable embedded reset control
On/Off
This option is turned on by default. When On,
the embedded reset controller initiates the reset
sequence when it receives a positive edge on the
phy_mgmt_clk_reset
input signal.
Disable this option to implement your own reset
sequence using the
tx_analogreset
,
rx_
analogreset
,
tx_digitalreset
,
rx_digital-
reset
, and
pll_powerdown
which are available as
top-level ports of the Low Latency Transceiver
PHY. When you design your own reset
controller, the
tx_ready
and
rx_ready
are not
top-level signals of the core. Another option is to
use Altera’s Transceiver PHY Reset Controller IP
Core to reset the transceivers. For more informa‐
tion, refer to the Transceiver PHY Reset Controller
IP Corechapter.
For more information about designing a reset
controller, refer to the User-Controlled Reset
Controller section in the Transceiver Reset Control
in Stratix V Devices in volume 2 of the Stratix V
Device Handbook.
UG-01080
2015.01.19
Additional Options Parameters
10-9
Low Latency PHY IP Core
Altera Corporation