Transceiver phy reset controller interfaces, Transceiver phy reset controller interfaces -6 – Altera Transceiver PHY IP Core User Manual
Page 583
Name
Range
Description
RX Channel
Enable RX channel reset control
On /Off
When On, the Transceiver PHY Reset
Controller enables the control logic and
associated status signals for RX reset. When Off,
disables RX reset control and status signals.
Use separate RX reset per channel On /Off
When On, each RX channel has a separate reset
input. When Off, uses a shared RX reset
controller for all channels.
RX digital reset mode
Auto, Manual,
Expose Port
Specifies the Transceiver PHY Reset Controller
behavior when the PLL lock signal is deasserted.
The following modes are available:
• Auto—The associated
rx_digital_reset
controller automatically resets whenever the
rx_is_lockedtodata
signal is deasserted.
• Manual—The associated
rx_digital_reset
controller is not reset when the
rx_is_
lockedtodata
signal is deasserted, allowing
you to choose corrective action.
• Expose Port—The
rx_manual
signal is a
top-level signal of the IP core. If the core
includes separate reset control for each RX
channel, each RX channel uses its respective
rx_is_lockedtodata
signal for automatic
reset control; otherwise, the inputs are
ANDed to provide internal status for the
shared reset controller.
rx_analogreset duration
1-999999999
Specifies the time in ns to continue to assert the
rx_analogreset
after the reset input and all
other gating conditions are removed. The value
is rounded up to the nearest clock cycle. The
default value is 40 ns.
rx_digitalreset duration
1-999999999
Specifies the time in ns to continue to assert the
rx_digitalreset
after the reset input and all
other gating conditions are removed. The value
is rounded up to the nearest clock cycle. The
default value is 4000 ns.
Transceiver PHY Reset Controller Interfaces
This section describes the top-level signals for the Transceiver PHY Reset Controller IP core.
The following figure illustrates the top-level signals of the Transceiver PHY Reset Controller IP core.
Many of the signals in the figure become buses if you choose separate reset controls. The variables in the
figure represent the following parameters:
•
•
—The number of PLLs
17-6
Transceiver PHY Reset Controller Interfaces
UG-01080
2015.01.19
Altera Corporation
Transceiver PHY Reset Controller IP Core