Altera Transceiver PHY IP Core - Manual (Page 239)

Signal Name Direction Signal Name
rx_rmfifodatainserted[-1:0]
Output When asserted, indicates that the RX
rate match block inserted an ||R||
column.
rx_rmfifodatadeleted[-1:0]
Output When asserted, indicates that the RX
rate match block deleted an ||R||
column.
rx_rlv[ -1:0]
Output When asserted, indicates a run length
violation. Asserted if the number of
consecutive 1s or 0s exceeds the
number specified in the MegaWizard
Plug-In Manager.
rx_recovered_clk[-1:0]
Output This is the RX clock which is
recovered from the received data
stream.
rx_byteordflag[-1:0]
Output This status flag is asserted high the
received data is aligned to the byte
order pattern that you specify.
Optional Reset Control and Status Interface
This topic describes the signals in the optional reset control and status interface. These signals are
available if you do not enable the embedded reset controller.
Table 9-19: Avalon-ST RX Interface
Signal Name Direction Description
pll_powerdown
Input When asserted, resets the TX PLL.
tx_digitalreset[-1:0]
Input When asserted, reset all blocks in the TX PCS. If
your design includes bonded TX PCS channels,
refer to Timing Constraints for Reset Signals when
Using Bonded PCS Channels for a SDC constraint
you must include in your design.
tx_analogreset[-1:0]
Input When asserted, resets all blocks in the TX PMA.
Note: For Arria V devices, while compiling a
multi-channel transceiver design, you
will see a compile warning (12020) in
Quartus II software related to the signal
width of tx_analogreset. You can safely
ignore this warning. Also, per-channel
TX analog reset is not supported in
Quartus II software. Channel 0 TX
analog resets all the transceiver
channels.
9-26 Optional Reset Control and Status Interface
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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