Altera Transceiver PHY IP Core - Manual (Page 43)

Signal Name Direction Description
tx_digitalreset[-1:0]
Input When asserted, reset all blocks in the TX PCS. If
your design includes bonded TX PCS channels,
refer to Timing Constraints for Reset Signals when
Using Bonded PCS Channels for a SDC constraint
you must include in your design.
tx_analogreset[-1:0]
Input When asserted, resets all blocks in the TX PMA.
Note: For Arria V devices, while compiling a
multi-channel transceiver design, you
will see a compile warning (12020) in
Quartus II software related to the signal
width of tx_analogreset. You can safely
ignore this warning. Also, per-channel
TX analog reset is not supported in
Quartus II software. Channel 0 TX
analog resets all the transceiver
channels.
tx_cal_busy[-1:0]
Output When asserted, indicates that the initial TX
calibration is in progress. It is also asserted if
reconfiguration controller is reset. It will not be
asserted if you manually re-trigger the calibration
IP. You must hold the channel in reset until
calibration completes.
rx_digitalreset[-1:0]
Input When asserted, resets the RX PCS.
rx_analogreset[-1:0]
Input When asserted, resets the RX CDR.
rx_cal_busy[-1:0]
Output When asserted, indicates that the initial RX
calibration is in progress. It is also asserted if
reconfiguration controller is reset. It will not be
asserted if you manually re-trigger the calibration
IP.
Related Information
• Timing Constraints for Bonded PCS and PMA Channels on page 17-10
• Transceiver Reset Control in Stratix V Devices
• Transceiver Reset Control in Arria V Devices
• Transceiver Reset Control in Cyclone V Devices
10GBASE-R PHY Clocks for Arria V GT Devices
The following figure illustrates Arria V GT clock generation and distribution.
UG-01080
2015.01.19
10GBASE-R PHY Clocks for Arria V GT Devices 3-19
10GBASE-R PHY IP Core Altera Corporation
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