Altera Transceiver PHY IP Core - Manual (Page 360)

Name Direction Description
tx_10g_fifo_pfull
[-1:0]
Output When asserted, indicates that the TX FIFO is partially
full. Synchronous to
tx_10g_coreclkin
.
tx_10g_fifo_empty
[-1:0]
Output TX FIFO empty flag. Synchronous to
tx_10g_clkout
.
This signal is pulse-stretched; you must use a synchron‐
izer.
tx_10g_fifo_pempty
[-1:0]
Output TX FIFO partially empty flag. Synchronous to
tx_10g_
clkout
. This signal is pulse-stretched; you must use a
synchronizer.
tx_10g_fifo_del
[-1:0]
Output When asserted, indicates that a word has been deleted
from the rate match FIFO. This signal is used for the
10GBASE-R protocol. This signal is synchronous to
tx_
10g_coreclkin
.
tx_10g_fifo_insert
[-1:0]
Output When asserted, indicates that a word has been inserted
into the rate match FIFO. This signal is used for the
10GBASE-R protocol. This signal is pulse-stretched, you
must use a synchronizer. This signal is synchronous to
tx_clkout
.
RX FIFO
12-62 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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