Altera Transceiver PHY IP Core User Manual
Page 664
Chapter
Document
Version
Changes Made
Stratix V Transceiver
Native PHY IP Core
2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support fo final for this IP core in
Table 12-1: Device Family Support.
• Added a new topic called Slew Rate Settings.
• Changed Enable rx_pma_bitslip port parameter to Enable rx_
clkslip port in Table 12-7: RX PMA Parameters.
• Changed the description of
rx_clkslip
port in Table 12-38:
Native PHY Common Interfaces.
• Changed the range of PPM detector threshold parameter to +/-
1000 in Table 12-6: RX PMA Parameters.
• Updated the description of
rx_10g_blk_sh_err
signal in 10G
PCS Interface section.
• Updated the description of Enable rx_std_signaldetect port
parameter with details for implementing SATA/SAS applica‐
tions.
• Updated the 10G PCS Interface section to indicate that 10G PCS
interface signals are used when phase compensation FIFO is in
FIFO mode.
• Added a note to Table: Status Flag Mappings for Simplified
Native PHY Interface regarding EDB and PAD characters.
Arria V Transceiver
Native PHY IP Core
2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support to final for this IP core in
Table 13-1: Device Family Support.
• Added note related to PMA Direct mode support for Arria V
devices.
• Changed the range of PPM detector threshold parameter to +/-
1000 in Table 13-6: RX PMA Parameters.
• Added a note related to compile warning (12020) in the descrip‐
tion of
tx_analogreset
signal.
• Added Table: Status Flap Mappings for Simplified Native PHY
Interface in Rate Match FIFO Parameters section.
21-4
Additional Information for the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core