Altera Transceiver PHY IP Core - Manual (Page 561)

Direct Write Reconfiguration
Follow these steps to reconfigure a transceiver setting using a series of Avalon-MM direct writes.
1. Write the logical channel number to the Streamer
logical
channel register.
2. Write Direct Mode, 2'b01, to the Streamer
control and status
register
mode
bits.
3. Write the offset address to the Streamer
offset
register.
4. Write the offset data to the Streamer
data
register.
5. Write the Streamer
control and status
register
write
bit to 1'b1 to initiate a write of all the data set
in the previous steps.
6. Repeat steps 3 through 5 if the offset data
length
is greater than 1. Increment the offset value by 1 for
each additional data record.
7. Read the
control and status
register
busy
bit. When the
busy
bit is deasserted, the operation has
completed.
In Steps 3 and 4, you must specify an offset value and offset data. You can determine the values of the
offset address and offset data by examining the data records specified in either the channel or PLL MIFs.
Figure 16-7: Sample MIF
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0
0 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0
1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0
Length = 3 Offset Value = 0
Offset Data
15 1110 0
For the sample data record, the length field specifies three data records. The offset value is 0, as indicated
by bits 10–0. The offset data are the three subsequent entries. The following example performs a direct
write in Streamer mode 1. This example writes the sample MIF into the Streamer module which writes
this data to logical channel 0.
Example 16-10: Streamer Mode 1 Reconfiguration
#Setting logical channel 0
write_32 0x38 0x0
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Setting Streamer to mode to 1
write_32 0x3A 4'b0100
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Setting Streamer offset register to the offset address
#In the example record, the first offset address is 0x0
write_32 0x3B 0x0
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Setting data register with the first data record
write_32 0x3C 16'b0010100000100000
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Writing first data to the Streamer
16-44 Direct Write Reconfiguration
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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