Altera Transceiver PHY IP Core - Manual (Page 698)

Date Document
Version
Changes Made
May 2011 1.2
• Added presets for the 2.50 GIGE and 1.25GIGE protocols.
• Moved dynamic reconfiguration for the transceiver outside of
the Custom PHY IP Core. The reconfiguration signals now
connect to a separate Reconfiguration Controller IP Core.
• Removed device support for Arria II GX, Arria II GZ, HardCopy
IV GX, and Stratix IV GX.
• Added the following parameters on the General tab:
• Transceiver protocol
• Create rx_recovered_clk port
• Force manual reset control
• Added optional
rx_rmfifoddatainserted
,
rx_rmfifodata-
delted
,
rx_rlv
, and
rx_recovered_clk
as output signals.
• Added
phy_mgmt_waitrequest
to the PHY management
interface.
• Renamed
reconfig_fromgxb
and
reconfig_togxb reconfig_
from_xcvr
and
reconfig_to_xcvr
, respectively.
• Corrected address for 8-Gbps RX PCS status register in Table 9–
18 on page 9–20.
• Added special pad requirement for Byte ordering pattern. Refer
to Table 9–6 on page 9–8.
• Clarified behavior of the word alignment mode. Added note
explaining how to disable all word alignment functionality.
Low Latency PHY Transceiver
May 2011 1.2
• Moved dynamic reconfiguration for the transceiver outside of
the Low Latency PHY IP Core. The reconfiguration signals now
connect to a separate Reconfiguration Controller IP Core.
• Moved dynamics reconfiguration for the transceiver outside of
the Custom PHY IP Core. The reconfiguration signals now
connect to a separate Reconfiguration Controller IP Core.
• Renamed the
tx_parallel_clk
signal
tx_clkout
.
Transceiver Reconfiguration Controller
May 2011 1.2
• Added Stratix V support. The Transceiver Reconfiguration
Controller is only available for Stratix IV devices in the
Transceiver Toolkit.
• Added sections describing the number of reconfiguration
interfaces required and restrictions on channel placement.
• Added pre- and post-serial loopback controls.
• Changed reconfiguration clock source. In 10.1, the Avalon-MM
PHY Management clock was used for reconfiguration. In 11.0,
the reconfiguration controller supplies this clock.
21-38 Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation Additional Information for the Transceiver PHY IP Core
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