Altera Transceiver PHY IP Core - Manual (Page 28)

Figure 3-4: 10GBASE-R PHY IP Core In Arria V GZ Devices
Data
Wiring
PLD-PCS & Duplex PCS
PCS-PMA
PCS
TX PMA
PMA
RX PMA & CDR
Generic
PLL
Reset
Controller
Transceiver
Reconfiguration
Controller
S
PMA + Reset Control & Status
(Memory Map)
Tx Serial
Rx Serial
S
Control & Status
(Optional or by
I/F Specification)
Avalon-ST
Streaming
Data
Tx Data
Rx Data
Transceiver Protocol
Arria V GZ Transceiver Protocol
To/From
XCVR
Avalon-MM Slave
Avalon-MM Master
S
M
Avalon-MM
Management
Interface
to Embedded
Controller
3-4 10GBASE-R PHY IP Core
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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