Altera Transceiver PHY IP Core - Manual (Page 127)

Addr Bit Acce
ss
Name Description
0x82
1 RO
HI_BER
High BER status. When set to 1, the PCS is reporting a
high BER. When set to 0, the PCS is not reporting a high
BER.
2 RO
BLOCK_LOCK
Block lock status. When set to 1, the PCS is locked to
received blocks. When set to 0, the PCS is not locked to
received blocks.
3 RO
TX_FULL
When set to 1, the
TX_FIFO
is full.
4 RO
RX_FULL
When set to 1, the
RX_FIFO
is full.
5 RO
RX_SYNC_HEAD_ERROR
When set to 1, indicates an RX synchronization error.
6 RO
RX_SCRAMBLER_ERROR
When set to 1, indicates an RX scrambler error.
7 RO
Rx_DATA_READY
When set to 1, indicates the PHY is ready to receive data.
1G/10 GbE GMII PCS Registers
This topic describes the GMII PCS registers.
Addr Bit R/W Name Description
0x90
9 RW
RESTART_AUTO_
NEGOTIATION
Set this bit to 1 to restart the Clause 37 Auto-Negotia‐
tion sequence. For normal operation, set this bit to 0
which is the default value. This bit is self-clearing.
12 RW
AUTO_
NEGOTIATION_
ENABLE
Set this bit to 1 to enable Clause 37 Auto-Negotiation.
The default value is 1.
15 RW
Reset
Set this bit to 1 to generate a synchronous reset pulse
which resets all the PCS state machines, comma
detection function, and the 8B/10B encoder and
decoder. For normal operation, set this bit to 0. This
bit self clears.
0x91
2 R
LINK_STATUS
A value of 1 indicates that a valid link is operating. A
value of 0 indicates an invalid link. If link synchroni‐
zation is lost, this bit is 0.
3 R
AUTO_
NEGOTIATION_
ABILITY
A value of 1 indicates that the PCS function supports
Clause 37 Auto-Negotiation.
5 R
AUTO_
NEGOTIATION_
COMPLETE
A value of 1 indicates the following status:
• The Auto-Negotiation process is complete.
• The Auto-Negotiation control registers are valid.
5-18 1G/10 GbE GMII PCS Registers
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
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