Altera Transceiver PHY IP Core - Manual (Page 68)

• An embedded processor mode to override the state-machine-based training algorithm. This mode
allows an embedded processor to establish link data rates instead of establishing the link using the
state-machine-based training algorithm.
The following figure illustrates the link training process, where the link partners exchange equalization
data.
Figure 4-3: TX Equalization for Link Partners
Rx
Encode
Handshake
Adapt
Tx
Eq
Decode Rx
Encode
Handshake
Adapt
Tx
Eq
Decode
Calculate
BER
Send Eq Change Eq Ack Change
Data Transmission Adaptation Feedback
1
2 3 4
TX equalization includes the following steps which are identified in this figure.
1. The receiving link partner calculates the BER.
2. The receiving link partner transmits an update to the transmitting link partner TX equalization
parameters to optimize the TX equalization settings
3. The transmitting partner updates its TX equalization settings.
4. The transmitting partner acknowledges the change.
This process is performed first for the V
OD
, then the pre-emphasis, the first post-tap, and then pre-
emphasis pre-tap.
The optional backplane daisy-chain topology can replace the spoke or hub switch topology. The following
illustration highlights the steps required for TX Equalization for Daisy Chain Mode.
4-12 10GBASE-KR PHY IP Core Functional Description
UG-01080
2015.01.19
Altera Corporation Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
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