Altera Transceiver PHY IP Core - Manual (Page 143)

Device Family Support
Stratix IV GX and GT devices-Soft or hard PCS and
PMA
Final
Stratix V devices-Soft PCS + PMA Final
Other device families No support
DXAUI
Stratix IV GX and GT Final
Other device families No support
XAUI PHY Performance and Resource Utilization for Stratix IV Devices
This section describes performance and resource utilization for Stratix IV Devices
The following table shows the typical expected device resource utilization for different configurations
using the current version of the Quartus II software targeting a Stratix IV GX (EP4SG230KF40C2ES)
device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the
nearest 100.
Table 6-3: XAUI PHY Performance and Resource Utilization—Stratix IV GX Device
Implementation Number of 3.125
Gbps Channels
Combinational
ALUTS
Dedicated Logic
Registers
Memory Bits
Soft XAUI 4 4500 3200 5100
Hard XAUI 4 2000 13000 0
XAUI PHY Performance and Resource Utilization for Arria V GZ and
Stratix V Devices
This section describes performance and resource utilization for Arria V GZ and Stratix V Devices.
For the Arria V GZ (5AGZME5K2F40C3) device, the XAUI PHY uses 1% of ALMs and less than 1% of
M20K memory, primary and secondary logic registers. Resource utilization is similar for Stratix V devices.
Parameterizing the XAUI PHY
Complete the following steps to configure the XAUI PHY IP Core:
1. Under Tools > IP Catalog, select the device family of your choice.
2. Under Tools > IP Catalog > Interfaces > Ethernet select XAUI PHY.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
4. Refer the following topics to learn more about the parameters:
UG-01080
2015.01.19
XAUI PHY Performance and Resource Utilization for Stratix IV Devices 6-3
XAUI PHY IP Core Altera Corporation
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