Altera Transceiver PHY IP Core - Manual (Page 288)

Optional TX and RX Status Interface for Deterministic Latency PHY
This section describes the optional TX and RX status interface settings for the Deterministic Latency PHY
IP core.
Table 11-15: Serial Interface and Status Signals
Signal Name Direction Signal Name
tx_ready
Output When asserted, indicates that the TX
interface has exited the reset state and is
ready to transmit.
rx_ready
Output When asserted, indicates that the RX
interface has exited the reset state and is
ready to receive.
pll_locked [
-1:0]
Output When asserted, indicates that the PLL is
locked to the input reference clock.
rx_bitslipboundaryselectout
[(5)-1:0]
Output Specifies the number of bits slipped to
achieve word alignment. In 3G (10-bit)
mode, the output is the number of bits
slipped. If no bits were slipped, the output is
0. In 6G (20-bit) mode, the output is (19 - the
number of bits slipped). If no bits were
slipped, the output is 19. The default value of
rx_bitslipboundaryselectout[4:0]
before alignment is achieved is 5'b01111 in
3G mode and 5'b11111 in 6G mode.
Optional Status Signals
tx_bitslipboundaryselect [(
5)-1:0]
Input This signal is used for bit slip word
alignment mode. It selects the number of bits
that the TX block must slip to achieve a
deterministic latency.
rx_disperr [(/)-1:0]
Output When asserted, indicates that the received
10-bit code or data group has a disparity
error.
rx_errdetect [(/)-1:0]
Output When asserted, indicates that a received 10-
bit code group has an 8B/10B code violation
or disparity error.
rx_syncstatus [(/)-1:0]
Output Indicates presence or absence of synchroni‐
zation on the RX interface. Asserted when
word aligner identifies the word alignment
pattern or synchronization code groups in
the received data stream. This signal is
optional.
11-20 Optional TX and RX Status Interface for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation Deterministic Latency PHY IP Core
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