Altera Transceiver PHY IP Core User Manual
Page 591
Figure 18-1: IP Cores Required for Designs Using the Fractional PLL
The following figure show the IP Cores you can instantiate to create designs that use a fractional PLL as
the TX PLL. The figure also illustrates the use of Transceiver PLL to instantiate CMU and ATX PLLs. The
MegaCore Library includes separate Transceiver PLL and Native PHY IP Cores for each V-Series Device
Family. This figure shows logical connectivity between IP Cores and does not reflect the physical location
of hardware in V-Series devices.
Altera Phased-Locked Loop
(ALTERA_PLL)
Fractional PLL
Native PHY
Transceiver PLL
CMU PLL
Transceiver PLL
ATX PLL
Serializer
Local Clock
Divider
(LCD)
Channel 1
(Stratix V and Arria V GZ, only)
Serializer
Local Clock
Divider
(LCD)
Channel 0
Designs that dynamically reconfigure the TX PLL between the CMU PLL and fractional PLL, must also
select Use external TX PLL in the Native PHY GUI and instantiate all PLLs externally as shown in the
figure above. Dynamic reconfiguration is only supported for non-bonded configurations. Dynamic
reconfiguration allows you to implement the following features:
• TX PLL reconfiguration between up to 5 input reference clocks
• PLL switching using the x1 clock lines within a transceiver triplet
• PLL switching using the x6 and xN clock lines when the TX channels are not in the same transceiver
bank
Note: It is not recommended to use fractional PLL in fractional mode for transceiver applications as a TX
PLL or for PLL cascading.
Related Information
•
Analog Settings for Arria V Devices
on page 19-2
•
Analog Settings for Arria V GZ Devices
on page 19-11
•
Analog Settings for Stratix V Devices
•
18-2
Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
UG-01080
2015.01.19
Altera Corporation
Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices