Altera Transceiver PHY IP Core User Manual
Page 672
Chapter
Document
Version
Changes Made
1G/10GbE Ethernet
PHY IP Core
2.5
Made the following changes:
• Corrected definition of
gxmii_rx_d
. This signal is synchronous
to
tx_clkout_1g
.
• Added frequency for
rx_recovered_clk[
. It's 257.8
MHz.
• Updated the descriptions of
rx_latency_adj_1g
and
tx_
latency_adj_1g
. Changed the width of these signals for all
references.
XAUI
2.5
Made the following changes:
• Added fact that both bits of the
reset_control
register at 0x042
self-clear.
• Added SDC Timing Constraints topic.
Interlaken
2.5
Added additional information about SDC timing constraints.
PHY IP Core for PCI
Express
2.5
Made the following changes:
• Removed the reference and description for
tx_invpolarity
and
rx_invpolarity
registers from Register Interface and Register
Descriptions section.
Custom PHY IP Core 2.5
Made the following changes:
• Added information on bit mapping for
tx_parallel_data
and
rx_parallel_data
.
• Changed the introduction of Optional Status Interfaces section.
This section applies for both TX and RX.
• Added a note related to auto-negotiation state machine in Rate
Match FIFO Parameters section.
• Updated the description of
rx_bitslip
signal.
• Added SDC Timing Constraints topic.
Low Latency PHY IP
Core
2.5
Added SDC Timing Constraints topic.
Deterministic
Latency PHY IP Core
2.5
Made the following changes:
• Updated the Channel Placement and Utilization for Deterministic
Latency PHY with details for Arria V and Arria V GZ devices.
• Updated the table for "Signal Definitions for rx_parallel_data
with and without 8B/10B Encoding".
• Added SDC Timing Constraints topic.
21-12
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core