Altera Transceiver PHY IP Core - Manual (Page 72)

Figure 4-7: FEC Functional Block Diagram
PCS
Transmit Encode
Scramble
Gearbox
PCS
Receive
Decode
Descramble
Block Sync
BER and Sync
Header Monitor
FEC (2112,2080) Encoder FEC (2112,2080) Decoder and Block Sync
PMA Sublayer
XGMII
PCS
Clause 49
FEC
Clause 74
PMA
Clause 51
PMA Service
Interface
MDI
XSBI
The FEC capability is encoded in the
FEC Ability
and
FEC Requested
bits of the base
Link Codeword
.
It is transmitted within a Differential Manchester Encoded page during Auto Negotiation. The link
enables the FEC function if the link partners meet the following conditions:
• Both partners advertise the FEC Ability
• At least one partner requests FEC
Note: If neither device requests FEC, FEC is not enabled even if both devices have the FEC Ability.
The TX FEC encoder (2112, 2080) creates 2112-bit FEC blocks or codewords from 32, 64B/66B encoded
and scrambled 10GBASE-R words. It compresses the 32, 66-bit words into 32, 65-bit words and generates
32-bit parity using the following polynomial:
g(x) = x 32 + x 23 + x 21 + x 11 + x 2 + 1
Parity is appended to the encoded data. The receiving device can use parity to detect and correct burst
errors of up to 11 bits. The FEC encoder preserves the standard 10GBASE-KR line rate of 10.3125 Gbps
by compressing the 32 sync bits from 64B/66B words. The TX FEC module is clocked at 161.1 MHz.
4-16 Forward Error Correction (Clause 74)
UG-01080
2015.01.19
Altera Corporation Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
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