Altera Transceiver PHY IP Core User Manual
Page 29
Figure 3-5: 10GBASE-R PHY IP Core In Stratix V Devices
Data
Wiring
PLD-PCS & Duplex PCS
PCS-PMA
PCS
TX PMA
PMA
RX PMA & CDR
Generic
PLL
Reset
Controller
PMA + Reset Control & Status
(Memory Map)
Tx Serial
Rx Serial
S
Control & Status
(Optional or by
I/F Specification)
Avalon-ST
Streaming
Data
Tx Data
Rx Data
Transceiver Protocol
Stratix V Transceiver Protocol
To/From
XCVR
Avalon-MM Slave
Avalon-MM Master
S
M
Avalon-MM
Management
Interface
to Embedded
Controller
Transceiver
Reconfiguration
Controller
S
The following table lists the latency through the PCS and PMA for Arria V GT devices with a 66-bit PMA.
The FPGA fabric to PCS interface is 64 bits wide. The frequency of the parallel clock is 156.25 MHz which
is line rate (10.3125 Gpbs)/interface width (64).
Table 3-1: Latency for TX and RX PCS and PMA Arria V Devices
PCS (Parallel Clock Cycles
PMA (UI)
TX
28
131
RX
33
99
The following table lists the latency through the PCS and PMA for Stratix V devices with a 40-bit PMA.
The FPGA fabric to PCS interface is 64 bits wide. The frequency of the parallel clock is 156.25 MHz which
is line rate (10.3125 Gbps)/interface width (64).
UG-01080
2015.01.19
10GBASE-R PHY IP Core
3-5
10GBASE-R PHY IP Core
Altera Corporation