Altera Transceiver PHY IP Core - Manual (Page 356)

Name Dir Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
rx_std_prbs_err Output Yes When asserted, indicates an error only
after the
rx_std_prbs_done
signal has
been asserted. This signal pulses for every
error that occurs. Errors can only occur
once per word.
To clear the PRBS pattern and deassert the
rx_std_prbs_done
signal by writing to the
memory-mapped register
PRBS Error
Clear
that you access through the
Transceiver Reconfiguration Controller IP
Core.
Miscellaneous
tx_std_elecidle[-1:0] Input When asserted, enables a circuit to detect a
downstream receiver. This signal must be
driven low when not in use because it
causes the TX PMA to enter electrical idle
mode with the TX serial data signals in
tristate mode.
rx_std_signaldetect[-
1:0]
Output No Signal threshold detect indicator. When
asserted, it indicates that the signal present
at the receiver input buffer is above the
programmed signal detection threshold
value. You must synchronize this signal.
Related Information
Transceiver Architecture in Arria V Devices
10G PCS Interface
The following figure illustrates the top-level signals of the 10G PCS. If you enable both the 10G PCS and
Standard PCS your top-level HDL file includes all the interfaces for both.
12-58 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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