Altera Transceiver PHY IP Core - Manual (Page 476)

Name Dir Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
rx_10g_data_valid
[-1:0]
Output Yes Active valid data signal with the following use:
• 10GBASE-R: Always high
• Interlaken: Toggles indicating when
rx_data
is
valid.
• Basic - Phase compensation: Toggles indicating
when
rx_data
is valid.
• Basic - Register: Toggles indicating when
rx_
data
is valid.
rx_10g_fifo_full
[-1:0]
Output No Active high RX FIFO full flag. Synchronous to
rx_
10g_clkout
. This signal is pulse-stretched; you
must use a synchronizer.
rx_10g_fifo_pfull
[-1:0]
Output No RX FIFO partially full flag. Synchronous to
rx_
10g_clkout
. This signal is pulse-stretched; you
must use a synchronizer.
rx_10g_fifo_empty
[-1:0]
Output Yes Active high RX FIFO empty flag,
rx_10g_fifo_pempty
[-1:0]
Output Yes Active high. RX FIFO partially empty flag,
rx_10g_fifo_align_clr
[-1:0]
Input Yes For the Interlaken protocol, this signal clears the
current word alignment when the RX FIFO acts as
a deskew FIFO. When it is asserted, the RX FIFO is
reset and searches for a new alignment pattern.
rx_10g_fifo_align_en
[-1:0]
Input Yes For the Interlaken protocol, you must assert this
signal to enable the RX FIFO for alignment.
rx_10g_align_val
[-1:0]
Output Yes For the Interlaken protocol, an active high
indication that the alignment pattern has been
found
Rx_10g_fifo_del
[-1:0]
Output No When asserted, indicates that a word has been
deleted from the TX FIFO. This signal is used for
the 10GBASE-R protocol. This signal is pulse-
stretched; you must use a synchronizer.
UG-01080
2015.01.19
10G PCS Interface 14-65
Arria V GZ Transceiver Native PHY IP Core Altera Corporation
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