Altera Transceiver PHY IP Core - Manual (Page 377)

Figure 13-1: Arria Native Transceiver PHY IP Core
CMU
PLLs
PMA
altera _xcvr_native_av
Transceiver Native PHY
Reconfiguration to XCVR
Reconfiguration from XCVR
TX and RX Resets
Calilbration Busy
PLL and RX Locked
RX PCS Parallel Data
TX PCS Parallel Data
CDR Reference Clock
TX PLL Reference Clock
RX Serial Data
to
FPGA fabric
TX PMA Parallel Data
RX PMA Parallel Data
TX Serial Data Serializer
De-
Serializer
Standard
PCS
(optional)
Serializer/
Clock
Generation
Block
Transceiver
Reconfiguration
Controller
Transceiver
PHY Reset
Controller
In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to
Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY
reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and
dynamic reconfiguration of the channel and PLLs.
You specify the initial configuration when you parameterize the IP core. The Transceiver Native PHY IP
Core connects to the “Transceiver Reconfiguration Controller IP Core” to dynamically change reference
clocks, PLL connectivity, and the channel configurations at runtime.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 13-1: Device Family Support
Device Family Support
Arria V devices Final
Other device families No support
13-2 Device Family Support
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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