Altera Transceiver PHY IP Core - Manual (Page 112)

Item Description
Product ID 0106
Vendor ID 6AF7
Device Family Support
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 5-2: Device Family Support
Device Family Support Supported Speed Grades
Arria V GZ devices–Hard PCS and
PMA
Final I3L, C3, I4, C4
Stratix V devices–Hard PCS and
PMA
Final All speed grades except I4 and C4
Other device families No support
Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and
Errata . Altera does not verify compilation with IP core versions older than the previous release.
Note: For speed grade information, refer to DC and Switching Characteristics for Stratix V Devices in the
Stratix V Device Datasheet.
Related Information
Stratix V Device Datasheet
1G/10 GbE PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the IP core in Arria V GZ and Stratix V
devices.
The following table shows the typical expected resource utilization for selected configurations using the
current version of the Quartus II software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The
numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers
reflect changes to the resource utilization reporting starting in the Quartus II software v12.1 release 28 nm
device families and upcoming device families.
Table 5-3: 1G/10 GbE PHY Performance and Resource Utilization
PHY Module Options ALMs M20K Memory Logic Registers
1GbE/10GbE - 1GbE only 300 0 600
UG-01080
2015.01.19
Device Family Support 5-3
1G/10 Gbps Ethernet PHY IP Core Altera Corporation
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