Altera Transceiver PHY IP Core User Manual
Page 265
Signal Name
Direction
Description
phy_mgmt_writedata[31:0]
Input
Input data.
phy_mgmt_readdata[31:0]
Output
Output data.
phy_mgmt_write
Input
Write signal.
phy_mgmt_read
Input
Read signal.
For more information about the Avalon-MM and Avalon-ST protocols, including timing diagrams, refer
to the
.
The following table describes the registers that you can access over the PHY Management Interface using
word addresses and a 32-bit embedded processor. The automatic reset controller automatically performs
the required reset sequence. After this reset sequence completes, you can manually initiate TX or RX
resets using the
reset_control
control register. You can also specify the clock data recovery (CDR)
circuit to lock to the incoming data or the reference clock using the
pma_rx_set_locktodata
and
pma_rx_set_locktoref
registers.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 10-13: Low Latency PHY IP Core Registers (Part 1 of 2)
Word Addr
Bits
R/W
Register Name
Description
Reset Control Registers–Automatic Reset Controller
0x041
[31:0]
RW
reset_ch_bitmask
Reset controller channel bitmask for digital
resets. The default value is all 1s. Channel
0x042
[1:0]
W
reset_control
(write)
Writing a 1 to bit 0 initiates a TX digital
reset using the reset controller module. The
reset affects channels enabled in the
reset_
ch_bitmask
. Writing a 1 to bit 1 initiates a
RX digital reset of channels enabled in the
reset_ch_bitmask
.
R
reset_status
(read)
Reading bit 0 returns the status of the reset
controller TX ready bit. Reading bit 1
returns the status of the reset controller RX
ready bit.
0x061
[31:0]
RW
phy_serial_loopback
_
Writing a 1 to channel <
n
> puts channel <
n
> in serial loopback mode. For informa‐
tion about pre or postCDR serial loopback
modes, refer to Loopback Modes.
PMA Control and Status Registers
10-18
Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation
Low Latency PHY IP Core