Altera Transceiver PHY IP Core User Manual
Page 686
Date
Document
Version
Changes Made
November 2012
1.8
• Created separate chapter for analog parameters that were
previously listed in the individual transceiver PHY chapters.
• Changed default value for
XCVR_GT_RX_COMMON_MODE_VOLTAGE
to 0.65V.
Introduction and Getting Started
June 2012
1.7
• Added brief discussion of the Stratix V and Arria V Transceiver
Native PHY IP Cores.
Getting Started
June 2012
1.7
• No changes from the previous release.
10GBASE-R PHY
June 2012
1.7
• Added the following QSF settings to all transceiver PHY:
XCVR_
TX_PRE_EMP_PRE_TAP_USER
,
XCVR_TX_PRE_EMP_2ND_POST_TAP_
USER
, and 11 new settings for GT transceivers.
• Added Arria V device support.
• Changed the default value for
XCVR_REFCLK_PIN_TERMINATION
from DC_coupling_internal_100_Ohm to AC_coupling.
• Changed references to Stratix IV GX to Stratix IV GT. This IP
core only supports Stratix IV GT devices.
• Added optional
pll_locked
status signal for Arria V and Stratix
V devices. Added optional
rx_coreclkin
.
• Added arrows Transceiver Reconfiguration Controller IP Core
connection to block diagram.
• Changed the maximum frequency of
phy_mgmt_clk
to 150 MHz
if the same clock is used for the Transceiver Reconfiguration
Controller IP Core.
• Added the following restriction in the dynamic reconfiguration
section: three channels share an Avalon-MM slave interface
which must connect to the same Transceiver Reconfiguration
Controller IP Core.
• Added example showing how to override the logical channel 0
channel assignment in Stratix V devices.
• Added table showing latency through PCS and PMA for Arria V
and Stratix V devices.
XAUI PHY
21-26
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core