Altera Transceiver PHY IP Core - Manual (Page 203)

Table 8-9: Transceiver Differential Serial Interface
Signal Name Direction Description
rx_serial_data[-1:0]
Input Receiver differential serial input data, <
n
> is the
number of lanes.
tx_serial_data[-1:0]
Output Transmitter differential serial output data <
n
> is the
number of lanes.
For information about channel placement, refer to “Transceiver Clocking and Channel Placement
Guidelines” in the Transceiver Configurations in Arria V GZ Devices or “Transceiver Clocking and
Channel Placement Guidelines” in the Transceiver Configurations in Stratix V Devices as appropriate.
Note: For soft IP implementations of PCI Express, channel placement is determined by the Quartus II
fitter.
For information about channel placement of the Hard IP PCI Express IP Core, refer to the Channel
Placement Gen1 and Gen2 and Channel Placement Gen3 sections in the Stratix V Hard IP for PCI Express
User Guide.
Related Information
• Transceiver Configurations in Arria V GZ Devices
• Transceiver Configurations in Stratix V Devices
• Stratix V Hard IP for PCI Express User Guide
PHY for PCIe (PIPE) Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the PHY IP Core for PCI Express PCS
and PMA features that are not part of the standard PIPE interface. You can use an embedded controller
acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.
The following figure provides a high-level view of this hardware; modules shown in white are hard logic
and modules shown in gray are soft logic.
UG-01080
2015.01.19
PHY for PCIe (PIPE) Register Interface and Register Descriptions 8-15
PHY IP Core for PCI Express (PIPE) Altera Corporation
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