Altera Transceiver PHY IP Core User Manual
Page 692
Date
Document
Version
Changes Made
December 2011
1.4
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
Custom
December 2011
1.4
• Added ×N and feedback compensation options for bonded
clocks.
• Added Enable Channel Interface parameter which is required
for dynamic reconfiguration of transceivers.
• Corrected formulas for signal width in top-level signals figure.
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
Low Latency PHY
December 2011
1.4
• Added option to disable the embedded reset controller to allow
you to create your own reset sequence.
• Added ×N and feedback compensation options for bonded
clocks.
• Fixed name of
phy_mgmt_reset
signal. Should be
phy_mgmt_
clk_reset
. Also, a positive edge on this signal initiates a reset.
• Added Enable Channel Interface parameter which is required
for dynamic reconfiguration of transceivers.
• Corrected formulas for signal width in top-level signals figure.
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
Deterministic Latency PHY
December 2011
1.4
• Removed Enable tx_clkout feedback path for TX PLL from the
General Options tab of the Deterministic Latency PHY IP Core
GUI. This option is unavailable in 11.1 and 11.1 SP1.
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
Transceiver Reconfiguration Controller
21-32
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core