Altera Transceiver PHY IP Core - Manual (Page 679)

Date Document
Version
Changes Made
Stratix V Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information
on how to instantiate an external PLL.
Arria V Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information
on how to instantiate an external PLL.
Arria V GZ Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information
on how to instantiate an external PLL.
Cyclone V Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information
on how to instantiate an external PLL.
Transceiver Reconfiguration Controller
March 2013 2.0 Made the following changes:
• Updated definition of
TX PLL select
at 0x4 in Table 16-21:
PLL Reconfiguration Offsets and Values.
• Changed Figure 16-5: MIF File Formatto match data in Table
16-26.
• Changed Example 16-11 to read the
busy
bit after each
command,
read_32 0x3a
.
• Added SDC timing constraints.
• Changed
RX Equalization Control
0x11 in Table 16-10: PMA
Offsets and Values to
RW
. This change is available starting with
Quartus II 12.1 SP1.
• Clarified encodings for
RX equalization DC gain
in Table
16-10: PMA Offsets and Values.
• Clarified encodings for pre-emphasis pre-tap and pre-emphasis
second post-tap in Table 16-10: PMA Offsets and Values.
• Clarified fact that you can only connect a single Transceiver
Reconfiguration Controller to a single transceiver PHY.
• Updated recommendations for use of DCD in Arria V and
Cyclone V devices. You should use DCD if the data rate is
greater than 4.9152 Gbps or if there is dynamic TX PLL
switching and the data rate is greater than 4.9152 Gbps. Updated
address map and illustration to include DCD function.
Transceiver Reset Controller
March 2013 2.0 Added
tx_ready
and
rx_ready
to Figure 17-1.
Transceiver PLL for Arria V, Arria V GZ, and Stratix V Devices
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core 21-19
Additional Information for the Transceiver PHY IP Core Altera Corporation
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