10g pcs interface, 10g pcs interface -58 – Altera Transceiver PHY IP Core User Manual
Page 469
Name
Dir
Synchro‐
nous to tx_
std_
coreclkin/
rx_std_
coreclkin
Description
tx_std_elecidle[
Input
When asserted, enables a circuit to detect a
downstream receiver. This signal must be
driven low when not in use because it
causes the TX PMA to enter electrical idle
mode with the TX serial data signals in
tristate mode.
rx_std_signaldetect[
1:0]
Output
No
Signal threshold detect indicator. When
asserted, it indicates that the signal present
at the receiver input buffer is above the
programmed signal detection threshold
value. You must synchronize this signal.
Related Information
10G PCS Interface
The following figure illustrates the top-level signals of the 10G PCS. If you enable both the 10G PCS and
Standard PCS your top-level HDL file includes all the interfaces for both.
14-58
10G PCS Interface
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core
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