Altera Transceiver PHY IP Core - Manual (Page 687)

Date Document
Version
Changes Made
June 2012 1.7
• Added the following QSF settings to all transceiver PHY:
XCVR_
TX_PRE_EMP_PRE_TAP_USER
,
XCVR_TX_PRE_EMP_2ND_POST_TAP_
USER
, and 11 new settings for GT transceivers.
• Added reference Transceiver device handbook chapters for
detailed explanation of PCS blocks.
• Changed the default value for
XCVR_REFCLK_PIN_TERMINATION
from DC_coupling_internal_100_Ohm to AC_coupling.
• Changed the maximum frequency of
phy_mgmt_clk
to 150 MHz
if the same clock is used for the Transceiver Reconfiguration
Controller IP Core.
• Added example showing how to override the logical channel 0
channel assignment in Stratix V devices.
• Expanded definition of External PMA control and configura‐
tion parameter.
• Added the following restriction in the dynamic reconfiguration
section: three channels share an Avalon-MM slave interface
which must connect to the same Transceiver Reconfiguration
Controller IP Core.
• Added note that
cal_blk_powerdown
register is not available for
Stratix V devices.
Interlaken PHY
June 2012 1.7
• Added support for custom, user-defined, data rates.
• Added the following QSF settings to all transceiver PHY:
XCVR_
TX_PRE_EMP_PRE_TAP_USER
,
XCVR_TX_PRE_EMP_2ND_POST_TAP_
USER
, and 11 new settings for GT transceivers.
• Changed the default value for
XCVR_REFCLK_PIN_TERMINATION
from DC_coupling_internal_100_Ohm to AC_coupling.
• Updated the definition of
tx_sync_done
. It is no longer
necessary to send pre-fill data before
tx_sync_done
and
tx_
ready
are asserted.
• Updated definition of
tx_datain_bp
.
• Added arrows indicating Transceiver Reconfiguration
Controller IP Core connection to block diagram.
• Changed the maximum frequency of
phy_mgmt_clk
to 150 MHz
if the same clock is used for the Transceiver Reconfiguration
Controller IP Core.
• Clarified signal definitions.
• Added the following restriction in the dynamic reconfiguration
section: three channels share an Avalon-MM slave interface
which must connect to the same Transceiver Reconfiguration
Controller IP Core.
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core 21-27
Additional Information for the Transceiver PHY IP Core Altera Corporation
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