Altera Transceiver PHY IP Core User Manual
Page 52
Word Addr
Bit
R/W
Name
Description
0x083
[5:0]
R
BER_COUNT[5:0]
For Stratix IV devices only, records
the bit error rate (BER). From block:
BER monitor
[13:6]
R
ERROR_BLOCK_COUNT[7:0]
For Stratix IV devices only, records
the number of blocks that contain
errors. From Block: Block synchron‐
izer
[14]
R
LATCHED_HI_BER
Latched version of
HI_BER
. From
block: BER monitor
[15]
R
LATCHED_BLOCK_LOCK
Latched version of
BLOCK_LOCK
. From
Block: Block synchronizer
Related Information
•
•
10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices
The 10GBASE-R PHY includes additional top-level signals when configured with an external modules for
PMA control and dynamic reconfiguration.
You enable this configuration by turning on Use external PMA control and reconfig available for Stratix
IV GT devices.
Table 3-17: External PMA and Reconfiguration Signals
Signal Name
Direction
Description
gxb_pdn
Input
When asserted, powers down the entire GT block.
Active high. For Stratix IV de
pll_pdn
Input
When asserted, powers down the TX PLL. Active high.
cal_blk_pdn
Input
When asserted, powers down the calibration block.
Active high.
cal_blk_clk
Input
Calibration clock. For Stratix IV devices only. It must
be in the range 37.5-50 MHz. You can use the same
clock for the
phy_mgmt_clk
and the
cal_blk_clk
.
pll_locked
Output
When asserted, indicates that the TX PLL is locked.
reconfig_to_xcvr[3:0]
Input
Reconfiguration signals from the Transceiver Reconfi‐
guration Controller to the PHY device. This signal is
only available in Stratix IV devices.
3-28
10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices
UG-01080
2015.01.19
Altera Corporation
10GBASE-R PHY IP Core