Altera Transceiver PHY IP Core User Manual
Page 693
Date
Document
Version
Changes Made
December 2011
1.4
• Added duty cycle distortion (DCD) signal integrity feature.
• Added PLL and channel reconfiguration using a memory initial‐
ization file (.mif).
• Added ability to reconfigure PLLs, including the input reference
clock or to change the PLL that supplies the high speed serial
clock to the serializer without including logic to reconfigure
channels.
• Corrected values for RX equalization gain. 0–4 are available.
• Corrected logical number in Interface Ordering with Multiple
Transceiver PHY Instances.
• Increased the number of channels that can share a PLL from 5 to
11 when feedback compensation is used.
• Increased the number of channels that can connect to the
Transceiver Reconfiguration Controller from 32 to 64.
• Added section on requirements for merging PLLs.
Introduction
November 2011
1.3
• Revised reset section. The 2 options for reset are now the
embedded reset controller or user-specified reset controller.
• Updated directory names in simulation testbench.
10GBASE-R PHY Transceiver
November 2011
1.3
• Added support for Stratix V devices.
• Added section discussing transceiver reconfiguration in Stratix
V devices.
• Removed
rx_oc_busy
signal which is included in the reconfigu‐
ration bus.
• Updated QSF settings to include text strings used to assign
values and location of the assignment which is either a pin or
PLL.
XAUI Transceiver PHY
November 2011
1.3
• The
pma_tx_pll_is_locked
is not available in Stratix V devices.
• Added base data rate, lane rate, input clock frequency, and
PLL type parameters.
• Updated QSF settings to include text strings used to assign
values and location of the assignment which is either a pin or
PLL.
• Added section on dynamic transceiver reconfiguration in Stratix
V devices.
• Removed Timing Constraints section. These constraints are
included in the HDL code.
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-33
Additional Information for the Transceiver PHY IP Core
Altera Corporation