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Altera Transceiver PHY IP Core User Manual

Page 674

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Chapter

Document

Version

Changes Made

Transceiver Reconfi‐

guration Controller

IP Core Overview

2.5

Made the following changes:
• Updated table for "Device Support for Dynamic Reconfigura‐

tion" to indicate that Arria

®

V and Cyclone

®

V devices support

TX PLL switching.

• Added a note in table for "PMA Offsets and Values" to indicate

possible methods to modify RX linear equalization settings.

• Added a note related to PLL reference clock status in Transceiver

Reconfiguration Controller DFE Registers section and ATX PLL

Calibration section.

• Updated the description of

mgmt_clk_clk

signal in Reconfigura‐

tion Management Interfaces section.

• Changed the name of "one time adaptation mode" to "triggered

dfe mode" and updated the Controlling DFE Using Register-Based

Reconfiguration section.

• Added a note in Transceiver Reconfiguration Controller EyeQ

Registers section.

• Added a note related to default values in Transceiver Reconfigu‐

ration Controller EyeQ Registers section.

Transceiver Reset

Controller IP Core

Overview

2.5

Made the following changes:
• Updated the description of

rx_manual

signal in Interfaces for

Transceiver PHY Reset Controller section.

• Updated the description of

pll_select

signal.

• Added a new section "Usage Examples for

pll_select

".

Analog Parameters

Set Using QSF

Assignments

2.5

Made the following changes:
• Updated definitions of

XCVR_RX_SD_ENABLE

,

XCVR_RX_SD_OFF

,

XCVR_RX_SD_ON

, and

XCVR_RX_SD_THRESHOLD

.These settings are

now available for SATA and SAS in addition to PCIe PIPE.

• Added documentation for

XCVR_ANALOG_SETTINGS_PROTOCOL

setting.

• Added warnings that there are restrictions

XCVR_TX_VOD

,

XCVR_

TX_PRE_EMP_1ST_POST_TAP

,

XCVR_TX_PRE_EMP_2ND_POST_TAP

,

and

XCVR_TX_PRE_EMP_PRE_TAP

for Stratix V and Arria V GZ

devices.

• Added warnings for restrictions on

XCVR_TX_PRE_EMP_1ST_

POST_TAP

for Arria V and Cyclone V devices.

• Changed default value for

XCVR_TX_VOD_PRE_EMP_CTRL_SRC

It's

DYNAMIC_CTL

for PCIe and

RAM_CTL

for other protocols.

• Corrected example showing how to override the

master_ch_

number

. The override must be applied to the transceiver

instance, not the top-level PHY wrapper.

21-14

Revision History for Previous Releases of the Transceiver PHY IP Core

UG-01080

2015.01.19

Altera Corporation

Additional Information for the Transceiver PHY IP Core

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