Altera Transceiver PHY IP Core User Manual
Page 522
Transceiver Reconfiguration Controller Performance and Resource
Utilization
This section describes the approximate device resource utilization for a the Transceiver Reconfiguration
Controller for Stratix V devices. The numbers of combinational ALUTs and logic registers are rounded to
the nearest 50.
Note: To close timing, you may need to instantiate multiple instances of the Transceiver Reconfiguration
Controller IP Core to the multiple transceiver PHYs in your design to reduce routing delays.
However, you cannot connect multiple Transceiver Reconfiguration Controllers to a single
transceiver PHY.
Table 16-3: Resource Utilization for Stratix V Devices
Component
ALUTs
Registers
Memory Blocks
M20Ks
Run Time
Transceiver Calibration Functions
Offset Cancellation
500
400
0
0
100 us/channel
Duty cycle calibration
350
400
0
0
70 us/channel
ATX PLL calibration
650
450
0
4
60 us/channel
Analog Features
EyeQ
300
200
0
0
-
AEQ
700
500
0
0
40 us/channel
Reconfiguration Features
Channel and PLL reconfi‐
guration
400
500
0
0
-
(16)
PLL reconfiguration (only) 250
350
0
0
Parameterizing the Transceiver Reconfiguration Controller IP Core
Complete the following steps to configure the Transceiver Reconfiguration Controller IP Core in the
MegaWizard Plug-In Manager:
1. Under Tools > IP Catalog, select the device family of your choice.
2. Under Tools > Interfaces > Transceiver PHY > Transceiver Reconfiguration Controller
3. Select the options required for your design.
4. Click Finish to generate your parameterized Reconfiguration Controller IP Core.
(16)
The time to complete these functions depends upon the complexity of the reconfiguration operation.
UG-01080
2015.01.19
Transceiver Reconfiguration Controller Performance and Resource Utilization
16-5
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation