Altera Transceiver PHY IP Core - Manual (Page 423)

FPGA Fabric Interface Width Arria V GZ Latency in UI
80 bits 164
The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of the
FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports.
However, depending upon the interface width selected not all bits on the bus will be active. The following
table lists which bits are active for each FPGA Fabric Interface Width selection. For example, if your
interface is 16 bits, the active bits on the bus are [17:0] and [7:0] of the 80 bit bus. The non-active bits are
tied to ground.
Table 14-10: Active Bits for Each Fabric Interface Width
FPGA Fabric Interface Width Bus Bits Used
8 bits [7:0]
10 bits [9:0]
16 bits {[17:10], [7:0]}
20 bits [19:0]
32 bits {[37:30], [27:20], [17:10], [7:0]}
40 bits [39:0]
64 bits {[77:70], [67:60], [57:50], [47:40], [37:30], [27:20],
[17:10], [7:0]}
80 bits [79:0]
Related Information
• Arria V Device Handbook Volume 2: Transceivers
• Device Datasheet for Arria V Devices
14-12 PMA Parameters for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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