Altera Transceiver PHY IP Core - Manual (Page 230)

Parameter Name GIGE-1.25 Gbps GIGE-2.50 Gbps
PCS-PMA Interface Width 10 10
Data rate 1250 Mbps 3125 Mbps
Input clock frequency 62.5 MHz 62.5 MHz
Enable TX Bitslip Off Off
Create rx_coreclkin port Off Off
Create tx_coreclkin port Off Off
Create rx_recovered_clk port Off Off
Create optional ports Off Off
Avalon data interfaces Off Off
Enabled embedded reset controller On On
Word Aligner Options
Word alignment mode Automatic
synchronization state
machine
Automatic synchronization state machine
Number of consecutive valid words
before sync state is reached
3 3
Number of bad data words before
loss of sync state
3 3
Number of valid patterns before
sync state is reached
3 3
Create optional word aligner status
ports
Off Off
Word aligner pattern length 10 10
Word alignment pattern 0101111100 0101111100
Enable run length violation
checking
Off Off
Run length - -
Rate Match Options
Enable rate match FIFO On On
Rate match insertion/deletion +ve
disparity pattern
10100010010101111100 10100010010101111100
Rate match insertion/deletion -ve
disparity pattern
10101011011010000011 10101011011010000011
8B/10B Options
UG-01080
2015.01.19
Presets for Ethernet 9-17
Custom PHY IP Core Altera Corporation
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