Sdc timing constraints, Simulation files and example testbench, Sdc timing constraints -27 – Altera Transceiver PHY IP Core User Manual
Page 167: Simulation files and example testbench -27
Table 6-17: Reconfiguration Interface
Signal Name
Direction
Description
reconfig_to_xcvr [(
1:0]
Input
Reconfiguration signals from the Transceiver Reconfigu‐
ration Controller. <
n
> grows linearly with the number of
reconfiguration interfaces. <
n
> initially includes the total
number transceiver channels and TX PLLs before
optimization/merging.
reconfig_from_xcvr [(
-1:0]
Output
Reconfiguration signals to the Transceiver Reconfigura‐
tion Controller. <
n
> grows linearly with the number of
reconfiguration interfaces. <
n
> initially includes the total
number transceiver channels before optimization/
merging.
Related Information
•
Transceiver Reconfiguration Controller to PHY IP Connectivity
•
Transceiver Reconfiguration Controller IP Core Overview
SDC Timing Constraints
The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP
apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V
Native PHY for details.
Related Information
SDC Timing Constraints of Stratix V Native PHY
on page 12-74
This section describes SDC examples and approaches to identify false timing paths.
Simulation Files and Example Testbench
Refer to “Running a Simulation Testbench” for a description of the directories and files that the Quartus
II software creates automatically when you generate your XAUI PHY IP Core.
Refer to the Altera Wiki for an example testbench that you can use as a starting point in creating your own
verification environment.
Related Information
•
Running a Simulation Testbench
•
UG-01080
2015.01.19
SDC Timing Constraints
6-27
XAUI PHY IP Core
Altera Corporation