Altera Transceiver PHY IP Core - Manual (Page 653)

Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in
Stratix IV and Stratix V Devices
This section lists the PHY IP Core for PCI Express PHY (PIPE) parameters and the corresponding
ALTGX megafunction parameters.
Table 20-4: Comparison of ALTGX Megafunction and PHY IP Core for PCI Express PHY (PIPE) Parameters
ALTGX Parameter Name (Default Value) CI Express PHY (PIPE)
Parameter Name
Comments
Number of channels Number of Lanes —
Channel width Deserialization factor —
Subprotocol Protocol Version —
Input clock frequency PLL reference clock
frequency
—
Starting Channel Number — Automatically set to 0.
Quartus II software
handles lane
assignments.
Enable low latency sync
pipe_low_latency_
syncronous_mode
—
Enable RLV with run length of
pipe_run_length_
violation_checking
Always on
Enable electrical idle inference functionality Enable electrical idle
inferencing
—
—
phy_mgmt_clk_in_mhz For embedded reset
controller to calculate
delays
UG-01080
2013.12.20
Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and
Stratix V Devices
20-7
Migrating from Stratix IV to Stratix V Devices Overview Altera Corporation
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