Xcvr_vcca_voltage, Xcvr_vccr_vcct_voltage – Altera Transceiver PHY IP Core User Manual
Page 631
Description
Specifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate with
1 representing the slowest rate.
Options
1–5
Assign To
Pin - TX serial data
XCVR_VCCA_VOLTAGE
Pin Planner and Assignment Editor Name
VCCA_GXB Voltage
Description
Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for
a GXB I/O pin. If you do not make this assignment the compiler automatically sets the correct
VCCA_GXB voltage depending on the configured data rate, as follows:
• Data rate <= 6.5 Gbps: 2_5V
• Data rate > 6.5 Gbps: 3_0V.
Options
• 2_5V
• 3_0V
Assign To
Pin - TX & RX serial data
XCVR_VCCR_VCCT_VOLTAGE
Pin Planner and Assignment Editor Name
VCCR_GXB
VCCT_GXB Voltage
Description
Refer to the Device Datasheet for Stratix V Devices for guidance on selecting a value.
Options
• 0_85V
• 1_0V
UG-01080
2015.01.19
XCVR_VCCA_VOLTAGE
19-37
Analog Parameters Set Using QSF Assignments
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)