Altera Transceiver PHY IP Core - Manual (Page 632)

Assign To
Pin - TX & RX serial data
Related Information
Stratix V Device Datasheet
Analog Settings Having Global or Computed Default Values for Stratix V Devices
The following analog parameters have global or computed default values. You may want to optimize some
of these settings. The default value is shown in bold type. For computed analog parameters, the default
value listed is for the initial setting, not the recomputed setting. The parameters are listed in alphabetical
order.
CDR_BANDWIDTH_PRESET
Pin Planner and Assignment Editor Name
CDR Bandwidth Preset
Description
Specifies the CDR bandwidth preset setting
Options
• Auto
• Low
• Medium
• High
Assign To
PLL instance
master_ch_number
Pin Planner and Assignment Editor Name
Parameter (Assignment Editor Only)
Description
For the PHY IP Core for PCI Express (PIPE), specifies the channel number of the channel acting as the
master channel for a single transceiver bank or 2 adjacent banks. This setting allows you to override the
default master channel assignment for the PCS and PMA. The master channel must use a TX PLL that is
in the same transceiver bank. Available for Gen1, Gen2, and Gen3 variants. The following example shows
how to override the default master channel for a Stratix V design. You must apply the
pma_bonding_master
override parameter on the Stratix V Transceiver Native PHY instance name. You
can use the same procedure for other devices.
19-38 Analog Settings Having Global or Computed Default Values for Stratix V Devices
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
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