Altera Transceiver PHY IP Core - Manual (Page 350)

Table 12-39: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding
The following table shows the signals within
tx_parallel_data
that correspond to data, control, and status
signals for a single 11-bit word. The
tx_parallel_data
bus is always 64 bits to enable reconfigurations between
the Standard and 10G PCS datapaths. If you only enable the Standard datapath, the 20, high-order bits are not
used.
TX Data Word Description
Signal Definitions with 8B/10B Enabled
tx_parallel_data[7:0]
TX data bus
tx_parallel_data[8]
TX data control character
tx_parallel_data[9]
Force disparity, validates disparity field.
tx_parallel_data[10]
Specifies the current disparity as follows:
• 1'b0 = positive
• 1'b1 = negative
Signal Definitions with 8B/10B Disabled
tx_parallel_data[7:0]
TX data bus
tx_parallel_data[10]
Unused
Table 12-40: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS
Parameterizations
The following table shows the valid 11-bit data words with and without the byte deserializer for single- and
double-word FPGA fabric to PCS interface widths.
Configuration Bus Used Bits
Single word data bus, byte deserializer disabled [10:0] (word 0)
Single word data bus, byte serializer enabled [32:22], [10:0] (words 0 and 2)
Double word data bus, byte serializer disabled [21:0] (words 0 and 1)
Double word data bus, byte serializer enabled [43:0] (words 0-3)
Table 12-41: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding
This table shows the signals within
rx_parallel_data
that correspond to data, control, and status signals.
RX Data Word Description
Signal Definitions with 8B/10B Enabled
rx_parallel_data[9:0]
RX data bus
rx_parallel_data[10]
Synchronization status
rx_parallel_data[11]
Disparity error
rx_parallel_data[12]
Pattern detect
12-52 Common Interface Ports for Stratix V Native PHY
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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